Advances in semiconductor manufacturing technology have led to the development of integrated circuits having multiple levels of interconnect. In such an integrated circuit, patterned conductive material on one interconnect level is electrically insulated from patterned conductive material on another interconnect level by films of material such as, for example, silicon dioxide. These conductive materials are typically a metal or metal alloy. Connections between the conductive material at the various interconnect levels are made by forming openings in the insulating layers and providing an electrically conductive structure such that the patterned conductive material from different interconnect levels are brought into electrical contact with each other. These electrically conductive structures are often referred to as contacts or vias.
Other advances in semiconductor manufacturing technology have lead to the integration of millions of transistors, each capable of switching at high speed. A consequence of incorporating so many fast switching transistors into an integrated circuit is an increase in power consumption during operation. One technique for increasing speed while reducing power consumption is to replace the traditional aluminum and aluminum alloy interconnects found on integrated circuits with a metal such as copper, which offers lower electrical resistance. Those skilled in the electrical arts will appreciate that by reducing resistance, electrical signals may propagate more quickly through the interconnect pathways on an integrated circuit. Furthermore, because the resistance of copper is significantly less than that of aluminum, the cross-sectional area of a copper interconnect line, as compared to an aluminum interconnect line, may be made smaller without incurring increased signal propagation delays based on the resistance of the interconnect.
But, the resistance of the copper interconnects will become significant once the width of the interconnects is less than around 100 nm. It is estimated that within the next five to ten years the minimum feature size will continue to shrink to below 45 nm. One approach to decreasing the resistance of copper lines having a width of less than 100 nm has been to anneal the copper to improve the conductive properties of the interconnect lines. But this has not been found sufficient. Embodiments of the current invention provide methods of reducing the resistivity of copper lines having a width of less than 100 nm, and in particular below 50 nm.